The invention relates to a substrate having a monocrystalline-silicon layer, an SiO2 layer arranged below and a silicon substrate arranged underneath, as well as to a method for its fabrication.
Such a substrate is referred to in the specialist field as an SOI substrate. The use of an SOI substrate instead of a customary silicon substrate for integrated semiconductor components offers a number of advantages. For instance, owing to the small thickness of the monocrystalline-silicon layer, which is customarily between 50 nm and 200 nm, active regions of the semiconductor components may be completely surrounded by insulating structures. To that end, installation trenches produced starting from one surface of the SOI substrate extend as far as the SiO2 layer. The complete insulation of the active regions avoids leakage currents between semiconductor components that neighbor one another. It is also possible to avoid short channel effects in transistors. A further advantage of using an SOI substrate is that capacitances at pn junctions are very small since no space-charge regions can be formed under the pn junctions, so that the switching speeds of the semiconductor components can be increased greatly and the semiconductor components"" power consumption can be lowered greatly. If a DRAM cell arrangement is produced in an SOI substrate, then any bit line capacitance can be reduced greatly for the same reason.
However, complete insulation of the active region also leads to negative effects, which are known as floating body effects. These effects are due to the fact that charge carriers created in the active region cannot be dissipated. This is particularly relevant to charge carriers produced in a channel region of a MOS transistor.
An SOI substrate, in which floating body effects are avoided, is described in Cuong T. Nguyen et al. xe2x80x9cQuasi-SOI MOSFETs Using Selective Epitaxy and Polishingxe2x80x9d, IEDM (1992), 341. The SiO2 layer is not continuous, but rather is interrupted by a silicon column. The silicon layer is not continuous either, but rather is embedded in an upper part of the SiO2 layer. The silicon column connects the silicon substrate to the silicon layer. A MOS transistor is arranged in the silicon layer in such a way that a channel region of the MOS transistor is connected to the silicon column. The channel region of the MOS transistor is hence connected to the silicon substrate through the silicon column, so that charge carriers produced in the channel region can be dissipated and floating body effects are avoided. To produce the SOI substrate, the SiO2 layer is produced on the silicon substrate and is patterned with the aid of two masked etching processes. During these, on the one hand, a recess, in which the silicon column will be produced at a later time, is produced as far as the silicon substrate. On the other hand, SiO2 is etched, in the environment of the recess, to a substantially smaller depth than the recess. By selective epitaxy and subsequent chemical-mechanical polishing until a surface of the SiO2 layer is exposed, the silicon column as well as, in the environment of the recess, the silicon layer is produced.
Y. Nishioka et al. xe2x80x9cGiga-bit Scale DRAM Cell with New Simple Ru/(Ba,Sr)TiO3/Ru Stacked Capacitors Using X-ray Lithographyxe2x80x9d IEDM (1995) 903, describes a DRAM cell arrangement in which a memory cell comprises a transistor and a capacitor. The transistor is a planar transistor, and its gate electrode is part of a word line that extends along a surface of a substrate in which the DRAM cell arrangement is arranged. Two transistors of two memory cells respectively share a common source/drain region that is connected to a bit line. The transistor has a further source/drain region, which is connected through a contact to a capacitor. The common source/drain region has a first part and a second part, which are respectively arranged between the word line and a neighboring word line and which adjoin one another. A connecting line drawn through the second part of the common source/drain region, the further source/drain region of the transistor and the further source/drain region of the neighboring transistor, is straight. The bit line is connected to the first part of the common source/drain region. Insulating structures laterally separate from each other source/drain regions of transistors of memory cells that neighbor one another along the word line. The insulating structures furthermore laterally separate from each other the further source/drain regions, which are connected to capacitors of memory cells that neighbor one another along the bit line.
The term xe2x80x9ccylinderxe2x80x9d denotes a body that is bounded by two parallel planes and a surface that is created by parallel displacement of a straight line along a space curve (cf. e.g. xe2x80x9cMeyer""s Lexikonxe2x80x9d). If the space curve is a circle, then the term xe2x80x9ccircular cylinderxe2x80x9d is used. In particular, a cuboid is also a cylinder. The term xe2x80x9ccylinderxe2x80x9d will also be used below to denote a body or a shape that deviates slightly from the mathematically rigorous cylinder. The deviation may be due e.g. to irregularities during etching processes, to deposition methods in which recesses are not completely filled in the vicinity of edges, or to the provision of auxiliary structures that are advantageous for a fabrication method and may e.g. narrow a part of the cylinder.
It is an object of the invention to provide a further SOI substrate in which the monocrystalline-silicon layer is connected to the silicon substrate, and which is suitable for an integrated semiconductor component in which floating body effects are avoided. It is also an object to provide a method for fabricating such an SOI substrate.
The object is achieved by an SOI substrate in which a recess is provided that cuts through a silicon layer and an SiO2 layer arranged below. An upper part of the recess, which part is arranged in the vicinity of the silicon layer, has a cylindrical shape with a horizontal first cross section. A lower part of the recess, which part is arranged in the vicinity of the SiO2 layer, is bulged relative to the upper part of the recess such that it has a cylindrical shape with a horizontal second cross section that is larger than the first cross section. A cylinder of insulating material has a horizontal cross section that corresponds to the first cross section. A lower part of the cylinder is arranged in the lower part of the recess. The bulge is configured such that it laterally surrounds the lower part of the cylinder. A conductive structure, which adjoins the silicon layer and a silicon substrate, on which the SiO2 layer is arranged, is arranged in the bulge.
The silicon layer is connected to the silicon substrate through the conductive structure.
The object is furthermore achieved by a method for producing an SOI substrate, in which a recess that cuts through a silicon layer and an SiO2 layer arranged below is produced in the SOI substrate by anisotropic etching. A lower part of the recess, which part is arranged in the vicinity of the SiO2 layer, is widened by isotropic etching of SiO2 selectively with respect to silicon so that it has a bulge relative to an upper part of the recess, which part is arranged in the vicinity of the silicon layer. Subsequently, conductive material is deposited substantially conformally and etched back until a bottom of the recess is exposed, so that a conductive structure, which adjoins the silicon layer and the silicon substrate, is produced in the bulge. Subsequently, insulating material is introduced into the recess so as to produce a cylinder, the lower part of which is arranged in the lower part of the recess and is laterally surrounded by the conductive structure.
The method may be carried out starting with commercially available SOI substrates, in which the conductive structure is subsequently produced. The production of the conductive structure does not require any elaborate process steps, such as selective epitaxy.
Examples of suitable conductive material for the conductive structure include metals, metal silicides or semiconductor material.
The conductive structure preferably consists of doped silicon, the conductivity type of which corresponds to the conductivity type of the silicon substrate and of the silicon layer. In this way, contact resistances between the conductive structure and the silicon substrate, or the silicon layer, are particularly small.
Since the conductive structure adjoins the silicon layer from below, the conductive material of the conductive structure has particularly little influence on a semiconductor component arranged in the silicon layer. This aspect also entails great latitude in the selection of the conductive material for the conductive structure.
The semiconductor component is, for example, a MOS transistor. In this case, the conductive structure connects a channel region of the MOS transistor to the silicon substrate.
Since the silicon layer is preferably between 50 and 200 nm thick, the MOS transistor is generally designed as a planar transistor.
To increase the packing density of an integrated circuit arrangement, to which the MOS transistor belongs, it is advantageous for the recess to cut through a source/drain region of the MOS transistor. In this case, a contact that connects with the source/drain region can additionally be produced in the recess.
To produce such a contact, the cylinder is, for example, first produced by depositing the insulating material and etching it back in such a way that the upper part of the recess is not completely filled. Subsequently, conductive material is deposited in such a way that the contact is produced over the cylinder.
Alternatively, the recess is arranged beside the source/drain region.
The MOS transistor can be part of a memory cell of a DRAM cell arrangement. A capacitor, which is connected to the MOS transistor, is provided as a further part of the memory cell. A gate electrode of the MOS transistor may be part of a word line that extends along the surface of the substrate.
To increase the packing density of the DRAM cell arrangement, i.e. to reduce the area required per memory cell, the source/drain region (referred to below as the xe2x80x9ccommon source/drain regionxe2x80x9d) is at the same time the source/drain region of a further MOS transistor, which belongs to a further memory cell and whose gate electrode is part of a word line that neighbors the word line. A further source/drain region of the MOS transistor is connected to the capacitor. The contact, which adjoins the common source/drain region, is connected to a bit line extending over the substrate.
To increase the packing density, it is advantageous for lateral faces of the word lines to be provided with insulating spacers, and for the contact to adjoin one of the spacers of the word line and one of the spacers of the neighboring word line. This arrangement can be produced by a method having a self-aligned etching step, i.e. a step without masks to be aligned. To that end, the word line is covered with a protective layer. During the production of the recess, silicon is etched selectively with respect to the protective layer and with respect to the spacers, so that the contact, whose lower part is produced in the recess, adjoins the spacer of the word line, the spacer of the neighboring word line and the common source/drain region. During this etching step, it is expedient to use a mask. However, the alignment tolerance of the mask is so great, owing to the protective layer and the spacers, that this may be considered as a self-aligned etching step.
A layout of the DRAM cell arrangement may correspond to the one in Y. Nishioka et al. (ibid.). Hence, it is possible to provide insulating structures which separate from each other the source/drain regions of the MOS transistors of memory cells that neighbor one another along the word line. The insulating structures furthermore separate from each other the further source/drain regions, which are connected to capacitors of memory cells that neighbor one another along the bit line. The common source/drain region has a first part and a second part, which are respectively arranged between the word line and the neighboring word line and which adjoin one another. The contact with the bit line is arranged in the first part of the common source/drain region. A connecting line drawn through the further source/drain region of the MOS transistor, the second part of the common source/drain region and the further source/drain region of the further transistor, is straight. To avoid leakage currents, it is advantageous for the insulating structures to respectively adjoin the surface of the substrate, and the silicon substrate.
The advantageous effects of the invention are independent of the layout of the DRAM cell arrangement.
The SiO2 layer is advantageously between approximately 100 nm and approximately 500 nm thick.